IBM Unveils the World's First 0.7-Nanometer Chip — Nearly 100 Billion Transistors on a Fingernail
The world's first sub-1nm logic chip
For over 40 years, chips moved forward by making transistors ever smaller — and the dimensions are now closing in on a single atom. This is the first crossing below 1 nanometer, and IBM's approach isn't to keep shrinking but to stand the transistors up and stack them.
- IBM unveiled the world's first sub-1nm chip technology, a node named 0.7 nanometers (7 angstroms), packing nearly 100 billion transistors into a fingernail-sized chip — about double the density of its 2021 2nm chip.
- The core innovation is a new transistor architecture, nanostack: instead of shrinking planar dimensions, it stacks transistors in 3D and staggers them — the industry's first three-dimensional nanosheet architecture.
- Three key moves: stack-and-stagger, 3D sequential integration, and per-layer materials for independent optimization.
- Manufacturability has been validated through experiments such as a functional CMOS inverter; the +50% performance or +70% efficiency are projections relative to 2nm — and it's one or the other.
- It targets generative AI, cloud infrastructure, and next-gen end devices; IBM says mass production in 5 years at the earliest, with a roadmap good for at least a decade of scaling.
To grasp the breakthrough, first see how hard the wall is
Crossing below 1 nanometer is a milestone because the old path really is running out of road. For decades, the way chips got faster was straightforward: make transistors smaller, fit more of them on the same chip, and watch compute and efficiency climb. The trouble is that transistor dimensions are now approaching the scale of a single atom; shrinking further in the plane is getting ever closer to physical limits, and this "just shrink it more" road is nearly out of room.
This time IBM didn't force its way down the old road — it switched dimensions: instead of cramming in the plane, it stacks vertically. In the figure below, click through four steps to see how it multiplies the transistor count in the same area.
The old way: transistors spread across one plane, so wanting more means each must shrink further. But we've now hit the "atom wall" — there's barely any room left to shrink.
nanostack's first move: stack up, and offset the rows. Add another layer of transistors atop the original and stagger the two layers (IBM calls them staggered channels) — same footprint, twice as many packed in.
Second move: different materials per layer. The upper batch of transistors can use materials different from the lower ones, each picking what suits it best, independently optimizing performance and power with no compromise — something a planar architecture simply can't offer.
The result: in the same fingernail-sized space, nearly 100 billion transistors — about double the density of the 2021 2nm chip.
It's like turning a single-story house on a plot of land into a split-level, multi-story building: the footprint (chip area) stays the same, but stacking upward houses more residents (transistors) — and each floor can even be fitted out as a different layout (different materials) as needed.
So how did IBM do it: nanostack's three moves
Stack transistors vertically — and stagger them
In traditional architectures, transistors are all crowded onto one plane, so wanting more means shrinking their size. nanostack stacks transistors in 3D along the vertical axis, with the upper and lower layers staggered. Same footprint, more transistors by stacking upward — the industry's first known three-dimensional transistor architecture based on nanosheet.
Staggering isn't random stacking: offsetting lets the connections, heat dissipation, and signal paths between layers be laid out more sensibly. IBM's VLSI 2026 paper is specifically about a "staggered-channel" SRAM cell design.
Not gluing two wafers together — integrating layer by layer
With stacking chips, the hard part was never the "stacking" — it's stacking precisely and usably. nanostack uses 3D sequential integration: atop an already-built lower layer, the upper transistors are integrated directly, step by step, rather than building two wafers separately and then aligning and bonding them — so the layers come out naturally aligned.
This has already been demonstrated in the lab with ultra-thin dielectric bonding, achieving full CMOS integration — not a design on paper, but a functional circuit that switches properly. This step is the make-or-break of "can it actually be built."
Each stacked layer uses its own optimal material
In a planar architecture, every transistor is forced to share one set of materials and processes, each compromising for the others. Once stacked into multiple layers, each layer can use a different material combination — the upper and lower transistors each pick the materials that suit them, independently optimizing performance and power without dragging each other down.
This is an extra degree of freedom unlocked by "stacking up," and the reason IBM defines it as a "structure + material" dual innovation: not just density stacked out of space, but the performance and efficiency headroom that material layering brings.
Already built and working in the lab
Each of the three experiments proves one thing:
| Validation | What it proves |
|---|---|
| CMOS integration via ultra-thin dielectric bonding | Layers can be joined into full CMOS with an ultra-thin dielectric — the stacked structure really can be built |
| Dual-channel engineering capability | Both the upper and lower channels in the stack can be controlled at once — multiple layers working together is feasible |
| Functional CMOS inverter | The most basic logic unit switches properly, and the switching performance meets expectations — not merely powered on |
Separately, at VLSI 2026, IBM showed nanostack shrinking SRAM (the on-chip high-speed cache) by 40%. The denser the SRAM, the more cache fits in the same area — exactly matching advanced AI workloads' appetite for "massive data, high bandwidth." This one points straight at AI chips.
Who benefits: what 0.7nm buys you
This chip targets the compute demands of generative AI, cloud infrastructure, and next-gen electronics. Relative to 2nm, its performance and efficiency are an "either/or" — it depends on how you use it, and you can't max both at once. Toggle below to feel the trade-off.
At the same power, compute faster. For AI, that means the same machine with higher training and inference throughput — running large models faster.
At the same performance, use less power. One of the hardest bottlenecks for AI data centers today is power and cooling — efficiency gains hit that pain point directly.
The density and efficiency gains mean, for two kinds of scenarios:
About double the density means nearly twice the compute in the same area — or, flipped around, the same compute at far lower power. The cost and cooling of AI training and inference are now bottlenecked mainly on power, so the efficiency side of the gain is worth the most.
With the same battery and form factor, phones, PCs, and edge devices can run stronger local AI models — or stretch their battery life longer.
Key figures
The following are vendor projections or roadmap, not measured:
| Figure | Meaning |
|---|---|
| +50% | Performance gain (vs. 2nm, projected, either/or with efficiency) |
| +70% | Efficiency gain (vs. 2nm, projected, either/or with performance) |
| 5 yrs, earliest | IBM's stated production timing (roadmap) |
| At least 10 yrs | How long the process roadmap can keep scaling |
IBM's process history
R&D takes place at the Albany semiconductor research center in New York, with ASML's High NA EUV lithography equipment arriving soon; partners include Lam Research, Tokyo Electron, and SCREEN.
We're not just making smaller transistors — we're reinventing how chips are built. Jay Gambetta, Director of IBM Research (IBM press release, 2026-06-25)